IC Substrate In-Plane Coefficient of Thermal Expansion (CTE) Determination Test

The in-plane coefficient of thermal expansion (CTE) of an IC substrate directly governs thermomechanical stress, warpage behavior, and solder joint reliability in advanced semiconductor packages. This article provides a complete technical guide to the IC substrate in-plane CTE determination experiment, covering sample preparation, TMA test procedures, applicable standards such as IPC-TM-650 and ASTM E831, data calculation methods, and typical acceptance criteria for BGA, FCCSP, and FCBGA package substrates.

Technical Overview

An IC substrate, also known as a package substrate, is the high-density interconnect platform that electrically and mechanically connects a semiconductor die to the printed circuit board. Because the substrate sits between the silicon chip, which expands at approximately 2.6 ppm/°C, and the motherboard, which typically expands at 14 to 17 ppm/°C, its thermal expansion behavior is one of the most decisive parameters in package reliability engineering.

The in-plane coefficient of thermal expansion, often designated as the X/Y-axis or XY CTE, describes the fractional change in length of the substrate in the plane of the board per unit change in temperature. It is expressed in ppm/°C and is calculated as the slope of the dimension-versus-temperature curve. A CTE mismatch between the die, substrate, molding compound, and printed circuit board generates cyclic stress during reflow soldering and thermal cycling, which can lead to die cracking, interfacial delamination, copper trace fracture, and solder ball fatigue.

In a CTE determination experiment, the material is heated at a controlled rate while its dimensional change is continuously recorded, typically with a thermomechanical analyzer (TMA). The measurement yields the CTE below the glass transition temperature (alpha-1), the CTE above Tg (alpha-2), and frequently the Tg itself, since the expansion curve shows a distinct change in slope at the transition point. The experiment is commonly performed in accordance with the following reference standards:

• IPC-TM-650 Method 2.4.24 for glass transition temperature and thermal expansion of printed boards by TMA
• ASTM E831 for linear thermal expansion of solid materials by thermomechanical analysis
• IPC-4101 slash sheet requirements for base laminate CTE acceptance limits
• JIS C 6481 test methods for copper-clad laminates used in IC substrates

Testing Samples

Core Laminate Samples

Core samples are rectangular strips cut from bare laminate panels of materials such as BT (bismaleimide triazine) glass, low-CTE epoxy glass, or specialized glass-fabric composites. Typical specimen dimensions are 6 to 10 mm in the measurement direction by 3 to 5 mm in width, at full panel thickness. Conventional BT glass cores exhibit an in-plane CTE of roughly 10 to 17 ppm/°C, while low-expansion cores designed for large-body flip-chip packages are engineered toward 6 to 10 ppm/°C to better match the silicon die.

Build-Up Film Samples

Photosensitive build-up dielectric films, such as ajinomoto build-up film (ABF) and comparable cycloaliphatic epoxy systems, are tested as laminated specimens on a carrier or as free-standing cured films. These materials are isotropic in the plane but have a low modulus, so a first heating scan is often used to relieve residual stress before the reported measurement. Typical in-plane CTE values for build-up films range from approximately 20 to 40 ppm/°C below Tg, depending on grade and cure condition.

Finished Multilayer IC Substrate Samples

Specimens cut from actual production substrates carry copper circuit patterns, via structures, and solder resist, so the measured value represents an effective composite CTE rather than the pure resin or laminate value. Because copper expands at roughly 17 ppm/°C, dense copper planes can shift the effective in-plane CTE of the finished substrate. Samples should be taken from both the machine (X, warp) and transverse (Y, fill) directions, and from multiple panel locations such as corners and center, to capture spatial variation.

Sample Preparation and Conditioning

Specimens must be cut cleanly without edge chipping, since burr fragments under the TMA probe introduce dimensional artifacts. Standard conditioning involves baking at 105 ± 3 °C for 2 hours to drive off absorbed moisture, cooling in a desiccator to room temperature, and then conditioning at 23 ± 2 °C and 50 ± 5 % relative humidity before testing. A minimum of three to five specimens per direction per material lot is recommended for statistical validity.

Testing Items

The in-plane CTE determination experiment for IC substrates typically includes the following measurement items:

• In-plane CTE below Tg (alpha-1) in the X direction and Y direction, in ppm/°C
• In-plane CTE above Tg (alpha-2) in the X direction and Y direction, in ppm/°C
• Glass transition temperature determined from the inflection point of the expansion curve
• Total expansion percentage over a specified temperature window, for example 30 to 260 °C
• Comparison of bare laminate CTE versus effective CTE of the patterned finished substrate
• Anisotropy ratio between X and Y direction expansion, relevant for glass-cloth-reinforced cores

Testing Methods

Thermomechanical Analysis (TMA)

TMA is the industry-standard technique for this experiment. The specimen is placed on a quartz platform and a low-force expansion probe, typically applying 10 to 50 mN, rests on its upper surface. The furnace is purged with nitrogen at 20 to 50 mL/min to prevent oxidation. The temperature program equilibrates the sample at approximately 30 °C, then ramps at 5 °C/min to an endpoint such as 260 °C or 300 °C, ensuring the scan passes completely through the Tg region. For in-plane measurement, the strip specimen is oriented so that its long axis lies along the measurement direction of the probe. Many laboratories run two consecutive heating scans and report data from the second scan to eliminate the effects of moisture evolution and residual stress relaxation.

Quartz Push-Rod Dilatometry

A vertical or horizontal quartz dilatometer can be used as an alternative for larger specimens or higher-temperature ranges. The method follows the same principle of measuring length change against temperature, and its results correlate well with TMA when specimen geometry and heating rate are harmonized. Dilatometry is particularly useful for cross-checking TMA values during material qualification disputes.

Optical and Non-Contact Methods

Non-contact techniques such as digital image correlation (DIC) and optical interferometry measure full-field in-plane strain without probe loading, which is advantageous for very thin build-up films and ultra-low-modulus dielectrics. Thermoelastic simulation inputs for package warpage modeling are increasingly validated with these methods, since they capture local expansion gradients around dense copper regions that a contact probe averages out.

Calculation and Data Evaluation

The in-plane CTE is calculated from the slope of the dimension-versus-temperature curve over a defined interval, using the relationship alpha equals the change in length divided by the initial length and the change in temperature, with the result multiplied by one million to express ppm/°C. Common reporting windows are 50 to 150 °C for alpha-1 and Tg plus 10 °C to Tg plus 50 °C for alpha-2. Tg is determined by the intersection of the tangent lines fitted to the pre-transition and post-transition expansion segments, following ASTM E831 and IPC-TM-650 2.4.24 conventions. With disciplined technique, repeatability within ±0.5 to 1 ppm/°C is achievable, and each report should state the specimen geometry, direction, heating rate, temperature interval, and scan number used.

Applications

In-plane CTE determination data from these experiments support nearly every stage of the IC substrate and package development cycle:

• Incoming material qualification and supplier lot acceptance for core laminates and build-up films in substrate fabrication plants
• Finite element warpage simulation inputs for FCBGA, FCCSP, chip-last, and 2.5D/3D package designs, where CTE mismatch directly predicts package deformation
• Board-level reliability correlation for thermal cycling profiles such as -40 to 125 °C and 0 to 100 °C, where cyclic expansion mismatch drives solder joint fatigue life
• Process window optimization for lamination, curing, and post-cure schedules, since incomplete cure manifests as elevated or drifting CTE values
• Failure analysis of delamination, die cracking, and trace fracture events by comparing retained samples against fresh material baselines
• Material selection studies for advanced applications including silicon interposers, system-in-package modules, embedded die substrates, and automotive high-reliability packages

FAQ

Why is in-plane CTE so critical for IC substrates?

The in-plane CTE controls the shear stress transferred to the die attach layer, the underfill, and the solder joints during thermal excursions. Because silicon expands at only about 2.6 ppm/°C, a substrate expanding at 15 ppm/°C imposes roughly six times more strain on the interconnect system during reflow and thermal cycling, directly reducing joint fatigue life and increasing warpage.

What in-plane CTE value is considered acceptable?

Acceptance depends on package type and die size. Conventional BT glass cores in the 10 to 17 ppm/°C range are adequate for small chip-scale packages, while large-body flip-chip substrates generally require low-CTE cores in the 6 to 10 ppm/°C range. The specification should always be agreed between the package designer and the substrate supplier based on warpage and reliability modeling.

How does the copper pattern affect the measured CTE?

Copper expands at approximately 17 ppm/°C and acts as a mechanical constraint embedded in the dielectric. Dense copper planes and thick power ground stacks raise the effective in-plane CTE of a finished substrate relative to the bare laminate, which is why both bare material and patterned product should be characterized separately.

Why do the first and second heating scans give different results?

The first scan typically shows higher apparent expansion due to moisture outgassing, residual stress relaxation from lamination, and additional crosslinking of partially cured resin. Standard practice is to report the second scan unless a specification requires otherwise, and the scan number must always be documented in the test report.

What temperature range and heating rate should be used?

A heating rate of 5 °C/min under nitrogen purge is the most common condition, with the scan typically running from near room temperature to 260 °C or 300 °C so that the full post-Tg segment is captured. The CTE itself is then calculated over explicitly stated sub-intervals, because a single number over the entire range would blend the alpha-1 and alpha-2 behaviors and mask the transition.